Extended Abstract
Introduction
Critical infrastructures such as power distribution, water networks, transportation control and emergency communications rely on embedded processors for monitoring and control, and these processors must remain functional when energy is scarce or supplied by backup sources. Hardware with very low power dissipation, small area and simple fabrication therefore supports infrastructure resilience. Quantum-dot cellular automata (QCA) is a transistor-less nanocomputing paradigm in which binary information is represented by cell polarization and propagated through Coulombic interaction without current flow, which makes it a promising candidate for such processors. The one-bit full adder is a key arithmetic block, because its area, delay and reliability directly influence ripple-carry adders, arithmetic logic units and other datapath structures. However, many compact QCA full adders achieve low cell counts only through multilayer crossings or rotated cells, which complicates fabrication. In our previous study, an optimized 12-cell three-input XOR (XOR3) gate based on half-distance placement and explicit cell interaction was proposed and verified by simulation and by a physical proof. The present study examines whether this gate can be turned, without structural change, into a complete single-layer, crossover-free full adder that remains competitive with recent designs. Its new contributions are the full-adder architecture and layout, the simulation results, the physical proof of the carry path and a systematic comparison with 2025–2026 designs.
Methodology
The logical architecture follows SUM = A ⊕ B ⊕ Cin and Cout = M(A, B, Cin). The XOR3 block of the earlier work is retained unchanged for SUM, while a three-input majority gate produces the carry. Inputs A and B reach the majority gate through two consecutive two-cell interconnections, a half-cell-shifted pair and a diagonal pair, each of which inverts the signal, so that both inputs arrive in their true form. The final layout contains 23 conventional, non-rotated cells (three inputs, two outputs and eighteen ordinary cells) in a single layer without wire crossings; five cells are assigned to Clock 0, nine to Clock 1 and nine to Clock 2. The circuit was simulated in QCADesigner 2.0.3 with the bistable engine (12,800 samples, convergence tolerance 0.001, radius of effect 65 nm, relative permittivity 12.9, clock high 9.8 × 10⁻²² J, clock low 3.8 × 10⁻²³ J, clock amplitude factor 2, 100 iterations per sample, 18 nm cells with 5 nm dots on a 20 nm pitch). Area was measured as the bounding rectangle of all cells, and latency was obtained from the number of clock zones between the inputs and the outputs. The carry path was further verified with the potential-energy method of Farazkish and co-workers, in which the Coulomb energy between electrons is summed for both polarization states of a cell and the lower-energy state is taken as the stable one.
Results and discussion
The layout occupies 174 nm × 151 nm, i.e., 26,274 nm² ≈ 0.026 µm² (displayed by QCADesigner as 0.03 µm²). Since the inputs are in Clock 0 and both outputs in Clock 2, the latency is 0.5 clock cycle and the area–delay product is about 0.013 µm²·cycle. The waveforms confirm all eight rows of the full-adder truth table, with polarization magnitudes of about ±0.888 for SUM and ±0.881 for carry. The energy analysis shows that for A = 1, B = 1 and Cin = 0 the carry cell has a total potential energy of 22.09 × 10⁻²⁰ J in the logic-1 state and 31.80 × 10⁻²⁰ J in the logic-0 state, so logic 1 is stable; the same analysis yields the correct majority output for all eight input combinations. Compared with the 2026 planar design of Bhuvaneswari and Yuvaraj (36 cells, 0.04 µm², 0.75 cycle), the proposed adder uses 36.1% fewer cells, about 35% less area and a lower latency. Relative to the single-layer design of Abdullah-Al-Shafi (46 cells, 0.04 µm², 0.25 cycle), it halves the cell count and reduces the area by about 35%, but it is slower. The three-layer design of Seyedi and co-workers (21 cells, 0.02 µm², 0.5 cycle) and the 14-cell adder/subtractor of Majeed are more compact, although the former relies on a multilayer structure. The main advantages of the present design are thus its single-layer, crossover-free implementation with conventional cells, its strong output polarization and the direct reuse of a validated XOR3 gate, whereas its main limitations are the absence of energy-dissipation and fault-tolerance analyses.
Conclusion
A compact single-layer QCA full adder has been developed as a circuit-level continuation of the authors’ earlier three-input XOR research. The design uses 23 conventional cells, occupies 0.026 µm², has a latency of 0.5 clock cycle and produces strongly polarized outputs; its correct operation was confirmed both by simulation and by a physical energy analysis of the carry path. The circuit can serve as a building block for low-power, compact processing units in resilient critical-infrastructure systems. Future work should quantify energy dissipation with QCADesigner-E or QCAPro, study robustness against cell omission, displacement and temperature variation, and extend the design to multi-bit ripple-carry adders.